An ideal S/H introduces no distortion in the conversion process and is accurately modeled as an ideal sampler. However, time-related degradations such as errors in the periodicity of the sampling process (“jitter”), nonlinear variations in the duration of the sampling aperture, and changes in the voltage held during conversion (“droop”) do occur in practical devices.

If the interpolation factor is I = 256, the A/D converter output can be obtained by averaging successive non-overlapping blocks of 128 bits. This averaging would result in a digital signal with a range of values from zero to 256 (b as 8 bits) at the Nyquist rate. The averaging process also provides the required anti-aliasing filtering.

The sampling of an analog signal is performed by a sample-and-hold (S/H) circuit. The sampled signal is then quantized and converted to digital form. Usually, the S/H is integrated into the (A/D) converter. The S/H is a digitally controlled analog circuit that tracks the analog input signal during the sample mode and then holds it fixed during the hold mode to the instantaneous value of the signal at the time the system is switched from the sample mode to the hold mode.

To avoid aliasing, we first filter out the out-of-band (fl, F J 2) noise by processing the wideband signal. The signal is then passed through the low pass filter and re-sampled (down sampled) at the lower rate. The down sampling process is called decimation.

The A/D converter begins the conversion after it receives a convert command. The sampling period T should be larger than the duration of the sample mode and the hold mode.

A digital-to-analog (D/A) converter (DAC) takes a digital sequence and produces at its output a voltage or current proportional to the size of the digital word applied to its input.

The noise power σn2 can be reduced by increasing the sampling rate to spread the quantization noise power over a larger frequency band (-Fs/2, Fs/2), and then shaping the noise power spectral density by means o f an appropriate filter.

The electronic device that performs this conversion from an analog signal to a digital sequence is called an analog-to-digital (A/D) converter (ADC).

The A/D converter begins the conversion after it receives a convert command. The time required to complete the conversion should be less than the duration of the hold mode of S/H.

The use of an S/H allows the A /D converter to operate more slowly compared to the time actually used to acquire the sample. In the absence of an S/H, the input signal must not change by more than one-half of the quantization step during the conversion, which may be an impractical constraint.