Computer Organization

Address Translation

Question 1
Marks : +2 | -2
Pass Ratio : 100%
The memory allocated to each page is contiguous.
True
False
Explanation:
Each page might be allocated memory deferentially but the memory for one page will be continuous.
Question 2
Marks : +2 | -2
Pass Ratio : 100%
The bits used to indicate the status of the page in the memory is called ______
Control bits
Status bits
Progress bit
None of the mentioned
Explanation:
These bits are used to store the status information of the program.
Question 3
Marks : +2 | -2
Pass Ratio : 100%
The _______ bit is used to indicate the validity of the page.
Valid bit
Invalid bit
Correct bit
None of the mentioned
Explanation:
The os first validates the page and then only moves from the page table.
Question 4
Marks : +2 | -2
Pass Ratio : 100%
The starting address of the page table is stored in __________
TLB
R0
Page table base register
None of the mentioned
Explanation:
The register is used to hold the address which is used to access the table.
Question 5
Marks : +2 | -2
Pass Ratio : 100%
The virtual memory bridges the size and speed gap between __________ and __________
RAM and ROM
RAM and Secondary memory
Processor and RAM
None of the mentioned
Explanation:
The virtual memory basically works as an extension of the RAM.
Question 6
Marks : +2 | -2
Pass Ratio : 100%
Whenever a request to the page that is not present in the main memory is accessed ______ is triggered.
Interrupt
Request
Page fault
None of the mentioned
Explanation:
When a page fault is triggered, the os brings the required page into memory.
Question 7
Marks : +2 | -2
Pass Ratio : 50%
The general purpose registers are combined into a block called as ______
Register bank
Register Case
Register file
None of the mentioned
Explanation:
To make the access of the registers easier, we classify them into register files.
Question 8
Marks : +2 | -2
Pass Ratio : 100%
The cache bridges the speed gap between ______ and __________
RAM and ROM
RAM and Secondary memory
Processor and RAM
None of the mentioned
Explanation:
The Cache is a hardware implementation to reduce the access time for processor operations.
Question 9
Marks : +2 | -2
Pass Ratio : 50%
The lower order bits of the virtual address forms the __________
Page number
Frame number
Block number
Offset
Explanation:
This gives the offset within the page table.
Question 10
Marks : +2 | -2
Pass Ratio : 100%
The higher order bits of the virtual address generated by the processor forms the _______
Table number
Frame number
List number
Page number
Explanation:
The higher order bits indicate the page number which points to one particular entry in the page table.